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RTL Design

Learning designing RTL chips for the feature with us

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Course Details

Duration Mode Timings Total hours
3 Months
Online / Offline
2 hrs per day
275 hours

Course Overview

Unix and C shell Scripting

• Unix commands.
• Variables.
• Flow control statements.
• Console and file I/O operations.
• Shell scripting for process management and Jobs’ management
Advanced Digital Design

• ASIC design flow.
• Number systems, Boolean algebra and minimization of expressions.
• Design of combinational circuits
• Design of sequential circuits.
• Design of state machines.
• Block level design and analysis of circuits.
Hardware Modeling Using Verilog

• Introduction to hardware Modeling Languages.
• Data types and Operators.
• Flow control statements.
• Behavioral and structural modeling.
• Procedural statements.
• Procedural blocks.
• Tasks and Functions.
• System tasks.
• Test benches.
• Design for Synthesis.
Concepts Lint And Clock Domain Crossing
Verification using Verilog

• Tasks and functions for directed testing.
• Self checking test benches.
• Code coverage.
Logic Synthesis and STA (Basics)

• Introduction to Synthesis and requirement of Synthesis.
• Design and Library objects.
• Constraining a design for Synthesis.
• Generating and analyzing timing reports.
• Optimizing design to meet constraints.
• Timing exceptions.

Logic Synthesis & STA, Low power Implementation, FV

Unix and C shell Scripting

• Unix commands.
• Variables.
• Flow control statements.
• Console and file I/O operations.
• Shell scripting for process management and Jobs’ management
TCL scripting

• Variables, operators and substitutions.
• Use of scalars, Indexed arrays and Hashes
• Predefined functions on scalars, Indexed arrays, Hashes and strings.
• Flow control statements.
• References.
• Sub routines.
• File I/O.
• Regular expressions.
• Logs’ and reports’ processing using TCL.
Digital Design & HDL Concepts
Logic Synthesis

• Introduction to Synthesis and requirement of Synthesis.
• Design and Library objects.
• Constraining a design for Synthesis.
• Generating and analyzing timing reports.
• Optimizing design to meet constraints.
Static Timing Analysis

• Introduction to Static Timing Analysis
• Writing Timing constraints(.sdc) for design.
• Setup. Hold timing analysis with Examples
• Multi clock domain and Multicycle path concepts,
• Timing Exceptions.
Low Power Design Implementation

• Introduction to Low power concepts.
• Low power design implementation.
• Hands on expierence in UPF script writing.
Open chat
Welcome to TSilicon VLSI
RTL Design Engineer