Physical Design Engineer

7892884679 admin@tsiliconvlsi.com

Physical Design

Mainly focused on giving complete hands-on experience to physical design and physical verification

Join this course

Course Details

Duration	Mode	Timings	Availability
16 Weeks	Online / Offline	2 hrs per day	Part time

Course Overview

General (PRE-REQUISITES)
• Digital Design and its industrial use. • CMOS, FET and MOS. Physics level. • Operating System – Linux/Unix, Shell Programming • SOC Design flow Methodologies

Synthesis (RTL to Netlist)
• Synthesis – RTL and constraints/STA • Constraints and SDC development and analysis • DFT and scan insertion in Synthesis • Multi Pass Synthesis

Parasitic extraction
• RC Extraction • Usage of Industry RC extraction tool

Place & Route (Netlist to OASIS / GDSII)
• Physical Design Methodology and step wise flow • Floor planning and Macro Placement • Power Network Synthesis, Analysis • Standard cells and Physical-only cells placement • Scan-Chain Optimization for Congestion reduction • Congestion Analysis and fixes • Timing Optimization techniques in placement stage • Static Timing Analysis – pre-clock Tree Synthesis stage • Clock Tree Synthesis and various methods • Routing of Signal, Clock nets • Physical Verification concepts

Signoff-static timing analysis
• Sign-off STA Checks • Industry standard tool base STA and debug • Timing Closure techniques, tips and tricks • ECO Implementation and loops

Logical equivalence check
• Formal Verification • Non-Equivalence, Unmapped, Aborted checks

Signoff concepts
• IR-Drop concepts • EM Analysis concepts • Antenna fixes, Standard cell fill and Metal Fill

Low power methodology
• Low Power concepts • Power Domain & UPF Methodology

TCL scripting
• TCL scripting concepts • Analysing design parameters, fixing design issues

General (post-implementation)
• Advanced concepts in Static Timing Analysis • Lower nodes Understanding

Open chat

Physical Design Engineer