RTL Design
Training focus will be on RTL coding using Verilog & VHDL, manual integration, developing the glue logic during integration, tool-based integration, linting, CDC, UPF, Synthesis and STA. RTL Integration course will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA.
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ASIC Verification Engineer
Mainly focused on enhancing the Design Verification skills needed by industry. The curriculum is designed to include the latest methodologies being adopted by industry. By end of the course, you will have hands on experience in design and verification with Verilog, system Verilog (SV) in UVM methodology.
Physical Design
Physical Design Training course mainly focused on giving complete hands-on experience to physical design training with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.
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Analog Layout
Analog Layout Design training course mainly focused on giving hands-on practical exposure in doing chip layout design for a given analog & mixed signal design. By end of the course you will learn to work in Linux environment, schematic entry in EDA tool, placement planning, analog and digital layout design, routing and physical verification checks like DRC, LVS for typical analog circuits such as Opamp, PLL, Bandgap, LDO and standard cells.