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Analog Layout Engineer

Mainly focused on giving practical exposure in doing chip layout design for a given analog & mixed signal design

Join this course

Course Details

Duration Mode Timings Availability
12 Weeks
Online / Offline
9-10 AM
Full time

Course Overview

Introduction

• What is IC
• IC Evolution
• VLSI Terminologies
• VLSI Design Flow
• Full custom Design
• Semiconductor Basics
• Industry tools for Layout Design
CMOS PROCESS

• Introduction to MOS transistor
• MOS transistor characteristics
• Introduction to Layout
• CMOS Inverter
• CMOS Process
• Layout design of Basic gates
• Stick diagram
• Scaling in Chips
Layout Design Concepts I

• MOS devices layout structure
• Layout techniques
• Parameterized Cells
Layout Design Concepts II

• Matching techniques
• Signal shielding
• Device Isolation
• Guardrings
• BJT Transistor
Layout Verification and Extraction

• Design Rule Checks (DRC)
• Layout Vs Schematic (LVS)
• Parasitics and Layout Extraction
DFM and Reliability

• ESD
• Latchup
• Issues with Interconnects
• Electromigration
INTRODUCTION TO FULL CHIP LAYOUT

• Floorplanning for Block level
• Floorplanning for Full chip level
Open chat
Welcome to TSilicon VLSI
Analog Layout Engineer